Methods and devices for light extraction from a group iii-nitride volumetric led using surface and sidewall roughening

ABSTRACT

A method of fabricating LEDs from a wafer comprising a substrate and epitaxial layers and having a substrate side and a epitaxial side, said method comprising: (a) applying a laser beam across at least one of said substrate side or said epitaxial side of said wafer to define at least one laser-scribed recess having a laser-machined surface; and (b) singulating said wafer along said laser-scribed recess to form singulated LEDs, said singulated LEDs having a top surface, a bottom surface, and a plurality of sidewalls, at least one of said sidewalls comprising at least a first portion comprising at least a portion of said laser-machined surface.

RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.15/226,656, filed on Aug. 2, 2016, which is a continuation-in-part ofU.S. application Ser. No. 14/632,755 filed on Feb. 26, 2015, now U.S.Pat. No. 9,406,843, issued Aug. 2, 2016, which is a continuation of U.S.application Ser. No. 13/781,633 filed Feb. 28, 2013, now U.S. Pat. No.9,000,466, issued Apr. 7, 2015, which is a continuation in part of U.S.application Ser. No. 12/861,765 filed Aug. 23, 2010, which claims thebenefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent ApplicationNo. 61/236,838 filed on Aug. 25, 2009, each of which is incorporated byreference in its entirety.

FIELD OF DISCLOSURE

The disclosure relates to the field of LED light chips, and moreparticularly to techniques for achieving high-performance lightextraction from an LED chip.

BACKGROUND

The present disclosure is directed to an improved approach for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chips. More particularly, disclosed herein are techniques forachieving high-performance light extraction from a Group III-nitridevolumetric LED chip using undulated slanted sidewalls and surfaceroughening.

In making LED chips, improving the performance of light extraction fromthe material is an important design consideration. In some situationspatterning or roughening of certain surfaces can improve lightextraction. And, in some situations the materials used in making LEDs(e.g., GaN, Sapphire, SiC) are laser-scribed, laser-shaped and otherwisemanipulated during process such that those processes result in shapingand roughening of the surfaces of the LED device and/or surroundingstructures. New shaping and roughening techniques are called for inorder to achieve high-performance light extraction when using GroupIII-nitride materials.

SUMMARY

Embodiments of the present disclosures are directed to improvedapproaches for achieving high-performance light extraction. Moreparticularly, disclosed herein are techniques for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chip using undulated slanted sidewalls and surface roughening.

The present disclosure provides improved techniques to address theaforementioned issues with legacy approaches. More specifically, thepresent disclosure provides a detailed description of die shaping anddie sidewall roughening techniques used to achieve high-performancelight extraction from Group III-nitride volumetric LED chips.

The methods refer generally to GaN-based light emitting diodes grown onsapphire, SiC or similar heteroepitaxial substrate. In a specificembodiment, the present techniques provide a device configuration with ahigh extraction geometry, and fabrication method thereof, for aGaN-based light emitting diode overlying a bulk-GaN containingsubstrate.

Volumetric chips (e.g., chips where the vertical-to-horizontal aspectratio of the chip is greater than 5%, and can be on the order of 100% orlarger) are advantageous, because they benefit from additionalextraction from the sidewalls (e.g., lateral surfaces) of the chip. Thishelps to extract glancing-angle light. In order to further increaselight extraction, one can modify the sidewall facets in order to breakthese quasi-guided trajectories. This can be done by shaping andtexturing of the sidewall facets.

Further details of aspects, objects, and advantages of the disclosureare described below in the detailed description, drawings, and claims.Both the foregoing general description of the background and thefollowing detailed description are exemplary and explanatory, and arenot intended to be limiting as to the scope of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described below are for illustration purposes only. Thedrawings are not intended to limit the scope of the present disclosure.This patent or application file contains at least one drawing executedin color. Copies of this patent or patent application publication withcolor drawings will be provided by the U.S. Patent and Trademark Officeupon request and payment of the necessary fee.

FIG. 1 is a chart characterizing backscattering behavior as a functionof polar angle of incidence for achieving high-performance lightextraction from a Group III-nitride volumetric LED chip using surfaceand sidewall roughening, according to some embodiments.

FIG. 2 is a simplified diagram of a model exhibiting backscatteringbehavior for achieving high-performance light extraction from a GroupIII-nitride volumetric LED chip using surface and sidewall roughening,according to some embodiments.

FIG. 3 is a chart characterizing backscattering behavior as a functionof polar angle of incidence with various roughening patterns forachieving high-performance light extraction from a Group III-nitridevolumetric LED chip using surface and sidewall roughening, according tosome embodiments.

FIG. 4 is a chart characterizing light extraction as a function of topsurface roughness for achieving high-performance light extraction from aGroup III-nitride volumetric LED chip using surface roughening,according to some embodiments.

FIG. 5 is a chart characterizing light extraction as a function of polaremission angle for achieving high-performance light extraction from aGroup III-nitride volumetric LED chip using surface roughening,according to some embodiments.

FIG. 6 is a chart characterizing light extraction as a function ofn-grid width for achieving high-performance light extraction from aGroup III-nitride volumetric LED chip using surface roughening,according to some embodiments.

FIG. 7 is a chart characterizing light extraction as a function of polaremission angle, and showing n-grid width examples for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chip using surface roughening, according to some embodiments.

FIG. 8 is a chart characterizing light extraction as a function of chipheight and showing examples varying lateral dimensions for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chip using surface roughening, according to some embodiments.

FIG. 9 is a chart characterizing extraction as a function of variedpolar and azimuthal angles for a smooth volumetric chip for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chip, according to some embodiments.

FIG. 10 is a chart showing light extraction as a function of variedpolar and azimuthal angles for a surface-roughened volumetric chip forachieving high-performance light extraction from a Group III-nitridevolumetric LED chip using surface roughening, according to someembodiments.

FIG. 11 is a chart showing light extraction as a function of variedpolar and azimuthal angles for top surface-roughness for a volumetricchip for achieving high-performance light extraction from a GroupIII-nitride volumetric LED chip using surface roughening, according tosome embodiments.

FIG. 12 shows images of LED chips formed by various cleaving alongdifferent crystallographic planes, according to some embodiments.

FIG. 13 is a chart showing light extraction as a function of variedpolar and azimuthal angles for 1D roughened sidewall surfaces for avolumetric chip for achieving high-performance light extraction from aGroup III-nitride volumetric LED chip using surface and sidewallroughening, according to some embodiments.

FIG. 14 is a chart showing light extraction as a function of variedpolar and azimuthal angles for 2D roughened sidewall surfaces for avolumetric chip having a triangular base for achieving high-performancelight extraction from a Group III-nitride volumetric LED chip usingsurface and sidewall roughening, according to some embodiments.

FIG. 15 is a chart showing light extraction for 1D roughened sidewallsurfaces as a function of sidewall angle for a volumetric chip having atriangular base for achieving high-performance light extraction from aGroup III-nitride volumetric LED chip using surface and sidewallroughening, according to some embodiments.

FIG. 16 is a chart showing light extraction for 2D roughened sidewallsurfaces as a function of sidewall angle for a volumetric chip having atriangular base for achieving high-performance light extraction from aGroup III-nitride volumetric LED chip using surface and sidewallroughening, according to some embodiments.

FIG. 17 is a chart showing light extraction under varied sidewall andtop roughness for a volumetric chip having a triangular base forachieving high-performance light extraction from a Group III-nitridevolumetric LED chip using surface and sidewall roughening, according tosome embodiments.

FIG. 18 is a chart showing light extraction under varied substrateabsorption for a volumetric chip having a triangular base for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chip using surface and sidewall roughening, according to someembodiments.

FIG. 19 is a simplified schematic diagram of a light emitting diodedevice having a top surface region with a textured surface characterizedby a surface roughness of about 80 nm to about 10,000 nm; and a lateralsurface region having a textured surface characterized by a surfaceroughness of about 80 nm to about 10,000 nm for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chip using surface and sidewall roughening, according to someembodiments.

FIG. 20 shows light extraction as a function of roughness, according tosome embodiments.

FIG. 21 shows the encapsulation gain performance of LED chips formed byvarious cleaving along different crystallographic planes, according tosome embodiments.

FIG. 22 depicts scanning electron microscope (SEM) images of LED chipsformed by various laser scribing processes, according to someembodiments.

FIG. 23 shows the lumen output performance of LED chips formed byvarious laser scribing processes, according to some embodiments.

FIG. 24A shows the beam profile of a multiple-beam laser ablation toolused in the singulation process of LEDs.

FIG. 24B depicts variations in chip shape geometry and correspondingimpact on light extraction, according to some embodiments.

FIG. 24C depicts a light extraction plot as plotted across of range ofchip shape geometries, according to some embodiments.

FIG. 25 a wafer having fabricated LEDs disposed on the substratesurface, according to some embodiments.

FIG. 26 shows a singulation technique that results die that has atriangular projection, according to some embodiments.

FIG. 27A depicts a top view of a die that has a triangular projection,according to some embodiments.

FIG. 27B depicts a side view of a die that has a triangular projection,according to some embodiments.

FIG. 27C depicts a side view of a die that has a triangular projection,according to some embodiments.

FIG. 28 shows process for using a staggered laser beam profile depictingvariation of pulse width and power, according to some embodiments.

FIG. 29 shows a side view of a die that has a roughened face, accordingto some embodiments, according to some embodiments.

FIG. 30 exemplifies roughness when illumination techniques are used toroughen a face of an LED die, according to some embodiments.

FIG. 31A exemplifies roughness when a lower concentration SAH chemicaletching is used instead of illumination techniques to roughen a face ofan LED die, according to some embodiments.

FIG. 31B exemplifies roughness when a higher concentration SAH chemicaletching is used instead of illumination techniques to roughen a face ofan LED die, according to some embodiments.

FIG. 32 shows aluminum etch rates across a range of SAH concentrationsin KOH, according to some embodiments.

FIG. 33 is a rendering of a triangular die formed using some of thedisclosed techniques, according to some embodiments.

FIG. 34A presents an elevated top view of a terraced tetragonal LED chipformed by various laser ablation techniques, according to someembodiments.

FIG. 34B presents an elevated top view of a slanted sidewall tetragonalLED chip formed by various laser ablation techniques, according to someembodiments.

FIG. 34C presents an elevated top view of an undulating slanted sidewalltetragonal LED chip formed by various laser ablation and etchingtechniques, according to some embodiments.

FIG. 34D presents a side view of an undulating slanted sidewalltetragonal LED chip formed by various laser ablation and etchingtechnique, according to some embodiments.

FIG. 35 depicts steps in a method for forming a volumetric LED chipusing laser ablation and scribing processes, according to someembodiments.

DETAILED DESCRIPTION

Various embodiments will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsare shown. Various aspects may, however, be embodied in many differentforms and should not be construed as limited to the embodiments setforth herein. Rather, these embodiments are provided so that thisdisclosure will be thorough and complete, and will fully convey thescope of the invention to those skilled in the art. Like referencenumerals refer to like elements throughout.

Embodiments of the present disclosures are directed to improvedapproaches for achieving high-performance light extraction from LEDchips. More particularly, disclosed herein are techniques for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chip by using laser ablation techniques to achieve sidewall slantingand surface roughening.

In making LED chips, improving the performance of light extraction fromthe material is an important design consideration. In some situationsthe shape of the device (e.g., as pertains to light extraction) and thepatterning or roughening of certain surfaces can improve lightextraction. And, in some situations the materials used in making LEDs(e.g., GaN, Sapphire, SiC) are scribed, sawed, cleaved and otherwisemanipulated during process such that those processes result inpatterning or roughening of the surfaces of the LED device and/orsurrounding structures. However, when Group III-nitride materials (e.g.,gallium nitride) is used, traditional cleaving or other manipulations donot necessarily result in patterning or roughening of the surfaces ofthe LED device and/or surrounding structures, and other techniques arecalled for in order to achieve high-performance light extraction.

Moreover, the manufacture of Group III-nitride volumetric LED chipsmight involve cleaving along certain selected planes (e.g., c-plane,m-plane), and certain processing techniques (e.g., laser scribing) mightbe used with the Group III-nitride material, thus further demandingadvances in the techniques to produce Group III-nitride volumetric LEDchips that exhibit high-performance light extraction from surface andsidewall roughening.

Therefore, there is a need for an improved approach for achievinghigh-performance light extraction from Group III-nitride volumetric LEDchips. In the approach to achieve high-performance light extraction fromsurface and sidewall roughening when using Group III-nitride materials,many discoveries have been made, which discoveries and embodimentsthereto are disclosed in detail below.

Reference is now made in detail to certain embodiments. The disclosedembodiments are not intended to be limiting of the claims. Variousembodiments will now be described more fully hereinafter with referenceto the accompanying drawings, in which exemplary embodiments are shown.Various aspects may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the inventionto those skilled in the art. Like reference numerals refer to likeelements throughout.

Embodiments of the present disclosure provide improved techniques toaddress the aforementioned issues with legacy approaches. Morespecifically, the present disclosure provides a detailed description ofsurface and sidewall roughening techniques used to achievehigh-performance light extraction from Group III-nitride volumetric LEDchips.

The methods refer generally to GaN-based light emitting diodes grown onsapphire, SiC or similar heteroepitaxial substrate. In an embodiment,the present techniques provide a device configuration with a highextraction geometry, and fabrication method thereof, for a GaN-basedlight emitting diode overlying a bulk-GaN containing substrate.

Volumetric chips (e.g., chips where the vertical-to-horizontal aspectratio of the chip is greater than 5%, and can be on the order of 100% orlarger) are advantageous, because they benefit from additionalextraction from the sidewalls (e.g., lateral surfaces) of the chip. Thishelps to extract glancing-angle light. In order to further increaselight extraction, one can modify the sidewall facets in order to breakthese quasi-guided trajectories. This can be done by texturing of thesidewall facets. One way to texture the sidewalls is to produce1-dimensional roughness, such as vertical striations.

Further, improvements in extraction efficiency can be achieved byimplementing 1-dimensional and 2-dimensional sidewall roughening. Insome embodiments, the extraction efficiency for a chip with toproughness is 70%. With combinations of 1D and 2D sidewall roughness,light extraction is boosted to ˜82%.

As used herein, the term GaN substrate is associated with GroupIII-nitride based materials including GaN, InGaN, AlGaN, or other GroupIII containing alloys or compositions that are used as startingmaterials. Such starting materials include polar GaN substrates (i.e.,substrate where the largest area surface is nominally an (h k l) planewhere h=k=0, and l is non-zero), non-polar GaN substrates (i.e.,substrate material where the largest area surface is oriented at anangle ranging from about 80 degrees to 100 degrees from the polarorientation described above towards an (h k l) plane where l=0, and atleast one of h and k is non-zero) or semi-polar GaN substrates (i.e.,substrate material where the largest area surface is oriented at anangle ranging from about +0.1 degrees to 80 degrees or 110 degrees 179.9degrees from the polar orientation described above towards an (h k l)plane where l=0, and at least one of h and k is non-zero). Of course,there can be other variations, modifications, and alternatives.

The high-refractive index of Group III-nitride based semiconductordevices results in a large fraction of emitted light beingtotally-internally reflected at the semiconductor/air orsemiconductor/encapsulant interface on the first pass. The embodimentscontained herein provides methods for enhancing the fraction of emittedlight from a light emitting diode device which escapes thesemiconductor/air or semiconductor/encapsulant interface on the firstpass, and thereby improving the overall external quantum efficiency ofthe light emitting diode device. This is achieved through texturing orroughening of the sidewalls or side-surfaces of a light emitting diodedevice chip by applying the methods described in the embodiments below,so as to enhance the extraction of light from these sidewalls orside-surfaces.

For high-power chips, a wafer-bonded geometry is often used for thermalmanagement. In this case the p-side of the chip is covered by areflective contact and light is mostly extracted though the top side. Toincrease light extraction, this top surface is typically roughened inorder to randomize light trajectories and avoid guiding of light.Scattering properties of a surface (e.g., surface roughness) improveslight extraction in an LED. The following discussions assume rougheningfeatures with an average lateral distance on the order of ˜1 μm, as istypically obtained by processes such as chemical etching orphoto-electro-chemical etching and present in commercial GroupIII-nitride LEDs. The parameter which drives the scattering strength inthe calculations shown below is the so-called filling fraction f, e.g.,the area coverage of the scattering features. A small filling fractioncorresponds to scattering features with narrow lateral dimensionsseparated by flat regions, while f>0.5 is representative of GaNroughness in some commercial LEDs. The scattering properties of such asurface are illustrated on FIG. 1, which represents the one-bouncebackscattering Sb (e.g., the amount of light which is sent back in thesemiconductor) for a typical embodiment of a rough surface. A lowbackscattering corresponds to a large forward-scattering, and hence alarge light extraction.

An important parameter in describing a rough surface is thecharacteristic size of the features forming the roughness. In typicalembodiments, this characteristic size is related to the wavelength oflight λ and the index of the LED material n. For instance, in someembodiments, the characteristic size is larger than 0.1 time λ/n andsmaller than 30 times λ/n. The roughness of the surface can further bedescribed in terms of the shape of features that form the roughenedsurface. For instance, the roughness can be one-dimensional (e.g.,linear striations) or two-dimensional (e.g., surface variations in bothin-plane directions). Further, two-dimensional roughness can be composedof a variety of shapes such as pyramidal features, truncated pyramidalfeatures, cylindrical features, square features, spherical features,elliptical features, or a combination of these shapes.

FIG. 1 is a chart characterizing backscattering behavior as a functionof polar angle of incidence for achieving high-performance lightextraction from a Group III-nitride volumetric LED chip using surfaceand sidewall roughening. As an option, the present model characterizingbackscattering behavior as a function of polar angle of incidence may beimplemented in the context of the architecture and functionality of theembodiments described herein. Also, the method for characterizingbackscattering behavior as a function of polar angle of incidence or anycharacteristic therein may be carried out in any desired environment.FIG. 1 shows that Sb becomes close to unity for angles larger than 70°.This indicates that extraction to the outside of the chip is notefficient, and that light will need many bounces to be extracted. FIG. 1illustrates backscattering of a typical patterned surface versus polarangle of incidence θ averaged over the azimuthal angle ϕ (see plot 102).Here the surface is a GaN/epoxy interface made of cylindrical rods(filling fraction f=0.3), height h averaged from 0.8 to 1.2, pitchaveraged from 0.8 to 1.2). All distances in units of the free wavelengthλ.

Contrary to intuition, typical ‘random’ surfaces in LEDs do notnecessarily fully randomize light trajectory—most notably, lightpropagating near glancing angles is poorly extracted/diffused, andmostly undergoes specular reflection. FIG. 2 schematically representsthis behavior.

FIG. 2 is a diagram of model exhibiting backscattering behavior forachieving high-performance light extraction from a Group III-nitridevolumetric LED chip using surface and sidewall roughening. As an option,the present model exhibiting backscattering behavior may be implementedin the context of the architecture and functionality of the embodimentsdescribed herein. As shown, the details of the roughness do not affectthese results for features of a given size. FIG. 2 shows the schematicbehavior of a typical roughened surface. Light propagating close tonormal incidence (thin lines) is efficiently extracted. However, forlight propagating near glancing angle (thick lines), only a smallfraction of the light is extracted (thick line) while a large fractionis backscattered.

FIG. 3 is a chart characterizing backscattering behavior as a functionof polar angle of incidence with various roughening patterns forachieving high-performance light extraction from a Group III-nitridevolumetric LED chip using surface and sidewall roughening. As an option,the present model characterizing backscattering behavior as a functionof polar angle of incidence with various roughening patterns may beimplemented in the context of the architecture and functionality of theembodiments described herein.

FIG. 3 illustrates structural features by comparing the scatteringbehavior of periodic structures having cylindrical and pyramidalfeatures. In this calculation, the rough features have similar sizes,and show similar scattering behavior. This result can be extended todisordered structures by use of a supercell model which considers aperiodic structure with a large period whose unit cell is composed ofseveral scattering elements of varying shape and size, and thusapproximates the description of a disordered rough surface. Again, usesuch of a supercell model shows a very similar scattering behavior tothat shown in FIG. 3. These scattering properties can be integrated to aray-tracing light extraction model in order to describe realistic LEDchips and understand how the scattering properties impact lightextraction. Below are described various applications of such a model toselected geometries of interest. FIG. 3 shows backscattering of variousrough surfaces versus polar angle of incidence q: (solid line 304):cylindrical rods (height averaged from 0.8 to 1.2). Dashed line 306:pyramids (height 1). Dotted line 302: pyramids (height 0.6). Alldistances in units of the free wavelength l. All structures have afilling fraction f=0.3.

Thin-Film Chips

Thin-film chips (where the ratio of vertical-to-horizontal dimensions isless than 5%, and often less than 1%) are strongly affected by thescattering behavior of the scattering surface. This is illustrated inFIG. 4 which shows the extraction efficiency Cex of a 1 mm×1 mm×5 μmchip (typical dimensions for commercial power chips) with top surfaceroughness, as a function of the reflectivity R of the p-mirror. In thissimple model, the p-mirror is the only source of loss. A large value ofR is necessary to obtain high Cex>80% due to the difficulty to extractglancing-angle light. Additional models (e.g., that model additionalcharacteristics beyond the model of FIG. 4) show similar results.

FIG. 4 is a chart characterizing light extraction as a function of topsurface roughness for achieving high-performance light extraction from aGroup III-nitride volumetric LED chip using surface and sidewallroughening. As an option, the present model characterizing lightextraction as a function of top surface roughness may be implemented inthe context of the architecture and functionality of the embodimentsdescribed herein. FIG. 4 shows a square thin-film chip (1 mm×1 mm×5 μm)with a top surface roughness and varying p-mirror reflectively (see line402).

In this simple model, the p-mirror is the only source of loss. A largevalue of R is necessary to obtain high Cex>80% due to the difficulty toextract glancing-angle light. This is illustrated in FIG. 5.

FIG. 5 is a chart characterizing light extraction as a function of polaremission angle (see line 502) for achieving high-performance lightextraction from a Group III-nitride volumetric LED chip using surfaceand sidewall roughening. As an option, the present model characterizinglight extraction as a function of polar emission angle may beimplemented in the context of the architecture and functionality of theembodiments described herein.

As shown, FIG. 5 details the extraction efficiency Cex(θ) versus thepolar angle of emission θ (averaged over the azimuthal angle ϕ, and fora p-mirror reflectivity R=90%), and shows a collapse of Cex at large θ.This situation is exacerbated when considering additional absorbingfeatures (such as n-electrodes) that are present in chips. FIG. 6illustrates this situation. FIG. 5 shows a square chip (1 mm×1 mm×5 μm)with a top surface roughness and R=90% p-mirror reflectively and detailsof extraction efficiency as a function of polar emission angle θ(averaged over the azimuthal angle of emission ϕ). Angle around 50° to85° are poorly extracted.

FIG. 6 is a chart characterizing light extraction as a function ofn-grid width (see line 602) for achieving high-performance lightextraction from a Group III-nitride volumetric LED chip using surfaceand sidewall roughening. As an option, the present model characterizinglight extraction as a function of n-grid width may be implemented in thecontext of the architecture and functionality of the embodimentsdescribed herein. Also, the method for characterizing light extractionas a function of n-grid width or any characteristic therein may becarried out in any desired environment. FIG. 6 shows a square chip (1mm×1 mm) with a top surface roughness and R=90% p-mirror reflectively,varying n-grid width.

The chip of FIG. 6 depicts a chip of similar dimensions but with asquare n-grid of pitch a=250 μm, and of low reflectivity (R=50%) andvarying grid width w. As w increases, Cex is strongly impacted—this isbecause glancing-angle light travels large lateral distances and has ahigh probability of reaching the lossy n-grid. Again, this is seen indetail in FIG. 7.

FIG. 7 is a chart characterizing light extraction as a function of polaremission angle (see line 702) and line 706), and showing n-grid widthexamples for achieving high-performance light extraction from a GroupIII-nitride volumetric LED chip using surface and sidewall roughening.As an option, the present model characterizing light extraction as afunction of polar emission angle, and showing n-grid width examples maybe implemented in the context of the architecture and functionality ofthe embodiments described herein. Also, the techniques forcharacterizing light extraction as a function of polar emission angle,and showing n-grid width examples or any characteristic therein may becarried out in any desired environment. FIG. 7 shows a square chip (1mm×1 mm) with top surface roughness and R=9-% p-mirror reflective anddetails of extraction efficiency as a function of polar emission angleθ. Full lines (see lin 702) refer to non-grid 704 and dashed lines (seeline 706) refer to 15 μm-wide n-grid 708.

FIG. 7 shows the same angle-dependent light extraction Cex(θ) as isshown in FIG. 5 (for w=15 μm), and where the suppression of Cex at largeθ is even more pronounced.

Surface-Roughened Volumetric Chips

Volumetric chips (e.g., chips where the vertical-to-horizontal aspectratio of the chip is greater than 5%, and can be on the order of 100% orlarger) are advantageous, because they benefit from additionalextraction from the sidewalls (e.g., lateral surfaces) of the chip. Thishelps to extract glancing-angle light.

FIG. 8 is a chart characterizing light extraction as a function of chipheight and showing examples of varying lateral dimensions for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chip using surface and sidewall roughening. As an option, thepresent model characterizing light extraction as a function of chipheight and showing examples varying lateral dimensions may beimplemented in the context of the architecture and functionality of theembodiments described herein.

FIG. 8 shows how increasing the thickness of a chip increases itsextraction efficiency. First we consider a 1×1 mm surface-roughenedchip, with p-mirror reflectivity R=90%. Increasing the thickness from 5μm to 250 μm boosts the extraction from ˜75% to ˜83%, becauselarge-angle light can now be extracted by the sidewalls (e.g., lateralsurfaces). However, substrate loss can be present and hinder thebeneficial effect of volumetric chips. If we assume a GaN absorptioncoefficient α=1 cm⁻¹, extraction is significantly impacted. This can beimproved upon by reducing the lateral dimensions of the chip: with thesame α, a 250×250 μm chip is about 4% more efficient than a 1 mm×1 mmchip. The beneficial impact of sidewalls for light extraction canfurther be improved by modifying the shape of the chip. For instance,using a chip with a triangular base and the same surface area enablesmore light trajectories to be extracted. From FIG. 8, the advantage ofvolumetric chips can be leveraged when the chip dimensions and shape arewell chosen, considering the losses in the chip. FIG. 8 shows extractionefficiency vs. chip height, for chips with top surface roughness andR=90% p-mirror reflectivity: (solid line 804) 1 mm×1 mm square chip, noabsorption in the GaN substrate; (dashed line 808) 1 mm×1 mm squarechip, GaN absorption coefficient a=1 cm⁻¹; (dotted line 806) 250 μm×250μm square chip, GaN absorption coefficient a=1 cm⁻¹; (dash-dotted line802) Triangular chip (lateral dimension 380 μm), GaN absorptioncoefficient a=1 cm⁻¹.

We note that while we have modeled particular chip designs in the above,and other models of chips, additional sources of loss can be considered,for example: substrate absorption, absorption of all the contacts (p-and n-electrodes and additional interlayers), active region absorption,etc. In some of the following descriptions, realistic values for suchlosses are modeled.

More insight can be gained into the light-extraction process of suchvolumetric chips by looking at the angle-resolved extraction diagramCex(θ,ϕ)—here it is relevant to consider both angles. For simplicity,let us first consider a smooth (non-roughened) chip.

FIG. 9 is a chart showing extraction as a function of varied polar andazimuthal angles for a smooth volumetric chip for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chip using surface and sidewall roughening. As an option, thepresent model extraction as a function of varied polar and azimuthalangles for a smooth volumetric chip may be implemented in the context ofthe architecture and functionality of the embodiments described herein.

FIG. 9 models a smooth GaN volumetric chip (triangular base 380 μm,height 200 μm) emitting into a silicone of index n=1.4. Extraction isonly possible into seven extraction cones (one for the top surface, andsix for the three sidewalls—either directly or after one in-planebounce), while all the rest of the light is guided and eventually lost.To improve the extraction of light, in volumetric chips, its top surfacecan be roughened, which roughening serves to break guided lighttrajectories. A similar surface roughening approach can also improvelight extraction in thin-film chips. FIG. 9 shows details of extractionvs. polar (q) and azimuthal (f) angles, for a smooth volumetric chipwith a triangular base (lateral dimension 380 μm, height 200 μm). Thedirection of emitted light is characterized by the in-plane reduced wavevectors kx and ky. High extraction is obtained into the top extractioncone 904 and the six sidewall extraction cones (e.g., see sidewallextraction cone 902). No extraction is possible outside of these cones.

FIG. 10 is a chart showing light extraction as a function of variedpolar and azimuthal angles for a surface-roughened volumetric chip forachieving high-performance light extraction from a Group III-nitridevolumetric LED chip using surface and sidewall roughening. As an option,the present model light extraction as a function of varied polar andazimuthal angles for a surface-roughened volumetric chip may beimplemented in the context of the architecture and functionality of theembodiments described herein.

As shown, FIG. 10 illustrates the modification of the angle-resolvedextraction diagram when top surface roughness is implemented: Extractionis allowed for angles outside of the extraction cones (e.g., seesidewall extraction cone 902). However, this is not perfectly efficientbecause light propagating at large angles is weakly randomized, as wasthe case for a thin-film chip. Large angles still display limitedextraction (e.g., poor extraction 1002). Such trajectories, which werefer to as “quasi-guided”, limit the extraction efficiency of a GaNvolumetric chip with top surface roughness. FIG. 10 shows details ofextraction vs. polar (q) and azimuthal (f) angles, for a volumetric chipwith a triangular base (lateral dimension 380 μm, height 200 μm) withtop surface roughness. Surface roughness enables extraction of some ofthe light outside of the extraction cones—however this effect islimited, especially at large angles.

FIG. 11 is a chart showing light extraction as a function of variedpolar and azimuthal angles for top surface-roughness for a volumetricchip for achieving high-performance light extraction from a GroupIII-nitride volumetric LED chip using surface and sidewall roughening.As an option, the present model light extraction as a function of variedpolar and azimuthal angles for top surface-roughness for a volumetricchip may be implemented in the context of the architecture andfunctionality of the embodiments described herein.

FIG. 11 shows the total extraction efficiency of a volumetric surfaceroughness, as the scattering efficiency of the top roughness is varied(see line 1102). The extraction saturates for larger values of thescattering efficiency, because the top roughness never fully breaksquasi-guided trajectories. Here we used the roughness filling fractionas the scattering parameter. A similar result is obtained whenincreasing the size of the scattering features from ˜500 nm to ˜1.5 μm.Therefore efficient scattering requires a filling fraction which is highenough (typically >0.5) and a feature size which is large enough(typically ˜1 μm). However even using an optimized roughness, lightextraction remains limited. FIG. 11 shows Cex vs. top surface roughnessfor a GaN LED with a triangular base (lateral dimension 380 μm, height200 μm) and with top surface roughness.

Sidewall-Roughened Volumetric Chips

In order to further increase light extraction, one can modify thesidewall facets in order to break these quasi-guided trajectories. Thiscan be done by texturing of the sidewall facets. One way to texture thesidewalls is to produce 1-dimensional roughness, such as verticalstriations. Such striations can naturally be obtained by using a diecleaving method along a proper crystal plane.

FIG. 12 depicts an image of LED die formed by various cleavings alongdifferent crystallographic planes. As an option, the present techniqueof cleaving along different crystallographic planes may be implementedin the context of the architecture and functionality of the embodimentsdescribed herein.

FIG. 12 shows the sidewall morphology for two LEDs on bulk GaNsubstrates which were cleaved with the same method but along twodifferent crystal planes (a-plane and m-plane, as shown). The naturalsidewall roughness obtained in a-plane devices translates experimentallyinto higher light extraction efficiency. Such roughness is expected toincrease light extraction by breaking the threefold in-plane symmetry oflight propagation in the chip (e.g., by randomizing the azimuthal angleof propagation ϕ). FIG. 12 shows scanning electron microscope images oftriangular chips cleaved along different crystallographic planes of aGaN substrate. The m-plane chip has relatively smooth sidewalls (e.g.,lateral surface 1204 ₂) while the a-plane chip has pronouncedone-dimensional roughness on its lateral surfaces (see lateral surface1204 ₁).

FIG. 13 is a chart showing light extraction as a function of variedpolar and azimuthal angles for 1D roughened sidewall surfaces for avolumetric chip for achieving high-performance light extraction from aGroup III-nitride volumetric LED chip using surface and sidewallroughening. As an option, the present model for light extraction as afunction of varied polar and azimuthal angles for 1D roughened sidewallsurfaces for a volumetric chip may be implemented in the context of thearchitecture and functionality of the embodiments described herein.

FIG. 13 shows how the angle-resolved extraction diagram of a chip ismodified by randomizing the in-plane angles. Some quasi-guidedtrajectories are broken, resulting in larger extraction efficiency. Asseen on FIG. 13 however, the polar propagation angles are not randomized(because the sidewall roughness is vertical, and thus does not breaksymmetry in the vertical direction) and some quasi-guided trajectoriesremain for intermediate angles. Another way to texture the sidewalls isto introduce a two-dimensional texture—e.g., to break the planarity ofthe sidewalls along two directions. FIG. 13 shows details of extractionvs. polar (q) and azimuthal (f) angles, for a volumetric chip with atriangular base (lateral dimension 380 μm, height 200 μm) with topsurface roughness and 1D sidewall roughness. Due to randomization of(f), extraction is improved for some large angles. The six sideextraction cones effectively become an extraction ring 1302. Extractionis still limited at intermediate angles.

FIG. 14 is a chart showing light extraction as a function of variedpolar and azimuthal angles for 2D roughened sidewall surfaces for avolumetric chip having a triangular base for achieving high-performancelight extraction from a Group III-nitride volumetric LED chip usingsurface and sidewall roughening. As an option, the present model forlight extraction as a function of varied polar and azimuthal angles for2D roughened sidewall surfaces for a volumetric chip having a triangularbase may be implemented in the context of the architecture andfunctionality of the embodiments described herein. FIG. 14 shows detailsof extraction vs. polar (q) and azimuthal (f) angles, for a volumetricchip with a triangular base (lateral dimension 380 μm, height 200 μm)with top surface roughness and 2D sidewall roughness. All angles areefficiently randomized, either by the top or the sidewall roughness,resulting in high extraction at all angles.

FIG. 14 shows the corresponding light extraction diagram. In such acase, both polar and azimuthal angles are randomized upon incidence onthe textured sidewall, which can further increase light extraction.Extraction is substantially improved over some embodiments following thelight extraction model of FIG. 13, especially in certain angulardomains.

FIG. 15 and FIG. 16 exemplify the improvement in extraction efficiencypredicted by implementing 1-dimensional and 2-dimensional sidewallroughening. With the loss parameters chosen, the extraction efficiencyfor a chip with only top roughness is 70%. 1D and 2D sidewall roughnessboost extraction to ˜74% and ˜82%, respectively.

FIG. 15 is a chart showing light extraction for 1D roughened sidewallsurfaces as a function of sidewall skewing angle for a volumetric chiphaving a triangular base for achieving high-performance light extractionfrom a Group III-nitride volumetric LED chip using surface and sidewallroughening. As an option, the present model for light extraction for 1Droughened sidewall surfaces as a function of sidewall angle for avolumetric chip having a triangular base may be implemented in thecontext of the architecture and functionality of the embodimentsdescribed herein. FIG. 15 shows Cex vs. one-dimensional sidewallroughness (the x-axis of this plot is the average angle of the sidewallswith respect to planar sidewalls) for a GaN LED with a triangular base(lateral dimension 380 μm, height 200 μm) and with top surface roughness(see line 1502).

FIG. 16 is a chart showing light extraction for 2D roughened sidewallsurfaces as a function of sidewall angle for a volumetric chip having atriangular base for achieving high-performance light extraction from aGroup III-nitride volumetric LED chip using surface and sidewallroughening. As an option, the present model for light extraction for 2Droughened sidewall surfaces as a function of sidewall angle for avolumetric chip having a triangular base may be implemented in thecontext of the architecture and functionality of the embodimentsdescribed herein. FIG. 16 shows Cex vs. two-dimensional sidewallroughness for a GaN LED with a triangular base (lateral dimension 380μm, height 200 μm) and with top surface roughness.

In comparing the light extraction of FIG. 15 to the light extraction ofFIG. 16, the improvements can be seen.

FIG. 17 is a chart showing light extraction under varied sidewall andtop roughness for a volumetric chip having a triangular base forachieving high-performance light extraction from a Group III-nitridevolumetric LED chip using surface and sidewall roughening. As an option,the present model for light extraction under varied sidewall and toproughness for a volumetric chip having a triangular base may beimplemented in the context of the architecture and functionality of theembodiments described herein.

FIG. 17 shows a 2-dimensional map of expected improvement by combiningsurface roughness and 2D sidewall roughness, for a variety of scatteringstrengths. Typical top surface roughness obtained by chemical or PECetching can be described by a scattering strength f>0.4. Therefore,complementing such a top surface roughness with a moderate sidewallroughness f>0.15 is sufficient to achieve optimal extraction. FIG. 17shows Cex vs. sidewall and top roughness for a GaN LED with a triangularbase (lateral dimension 380 μm, height 200 μm) and with 2-dimensionaltop and sidewall surface roughness.

In the following embodiments, “texturization” or “roughness” describesan optical surface which deviates from planarity. The roughness may berandom, periodic (as in the case of a photonic crystal for instance) orpseudo-periodic. The roughness may be produced by a variety of means,including chemical etching, electro-chemical etching,photo-electro-chemical etching, patterning and dry etching, regrowth ofsemiconductor material over a patterned interface, roughness due to asawing/cleaving/laser scribing singulation process.

In one embodiment, the singulation process (which may combine laserscribing, sawing and cleaving) produces sidewall roughness.

In one embodiment, the present method and device includes a gallium andnitrogen (e.g., GaN) containing substrate having roughened regionsvertically oriented with respect to a pair of electrode faces. In anembodiment, the electrode faces are configured on a c-plane. Preferably,the substrate is separated by way of scribing, which occurs using alaser scribing process having a short wavelength laser. The beam ablatesby pulsing electromagnetic radiation on selected portions of the galliumand nitrogen containing substrate. The beam scribes the substrate alongthe a-plane. Preferably, the streets between devices are configured fromabout 1 micron to about 30 microns, although there can be variations.Each of the scribe regions has a width of 5 microns to 10 microns. Thescribe regions are formed using a UV laser configured with a 355 nmsource and an output power of 30 mW to 300 mW, but there can be otherconfigurations. The laser pulses are in the nanosecond regime, e.g., 2ns to 100 ns. The laser device and beam ablates a portion of the galliumand nitrogen containing material. The devices are later separated usinga break process along the scribe lines causing formation of theroughened regions, which are substantially m-plane in characteristic andforms the vertically oriented facets. Each of the m-faces has width of afew microns, but can also be other dimension. Additionally, each of thefacets has a peak region surrounded by troughs, when viewed from thec-plane direction. Optionally, the method subjects the scribe region toa selective etchant to remove any light absorbing slag material, whichmay be a by-product from the laser scribing process. Depending on thelaser pulsing frequency, stage speed, and chemistry used for removingthe by-product from the laser scribe process, a 2D roughness region withequal depth to the laser scribe can be created on the sidewalls of thedevice to greatly enhance light extraction. The selection of thechemistry for removal of the by-products is extremely important as somechemistry will tend to look for crystal plans and smooth out the region,while others induce roughness such as KOH. In some embodiments forcreating 2D roughness regions, the process creates two distinct regionson the sidewalls.

In some embodiments, the same procedure as above is employed. However,the laser ablation process is sufficient to fully ablate the substrateand produce full device singulation, so that no subsequent breaking stepis required. In such embodiments, the 2D roughness region created by thelaser ablation covers a large fraction, up to the totality, of thesidewalls.

In some embodiments, the LED is made of bulk GaN and has the shape of aprism with a triangular base. The top surface and the sidewalls alldisplay 2-dimensional roughness, with a roughness feature size on theorder of 1-2 microns and a roughness surface coverage larger than 0.5.

In another embodiment, the LED is made of bulk GaN and has the shape ofa prism with a triangular base. The top surface displays 2-dimensionalroughness, with a roughness feature size on the order of 1-2 microns anda roughness surface coverage larger than 0.5. The sidewalls displayvertical striations (1D roughness) with a characteristic distance of 1-5μm.

FIG. 18 is a chart showing light extraction under varied substrateabsorption for a volumetric chip having a triangular base for achievinghigh-performance light extraction from a Group III-nitride volumetricLED chip using surface and sidewall roughening. As an option, thepresent light extraction model 1802 is plotted across varied substrateabsorption for a volumetric chip having a triangular base.

FIG. 18 describes the impact of absorption coefficient on extractionefficiency. The Group III-nitride substrate has a crystal orientationsuch that its sidewalls can easily be roughened. FIG. 18 shows Cex vs.GaN substrate absorption a for a triangular chip (lateral dimension 380μm, height 200 μm) with top surface roughness.

According to some embodiments:

-   -   Only some of the sidewalls are roughened.    -   The sidewalls are slanted and roughened.    -   The LED is grown on a bulk Group III-nitride substrate, and the        resulting vertical-to-horizontal aspect ratio of the LED chip is        larger than 5%.    -   The LED is grown on a foreign substrate, but the Group        III-nitride layer is thick enough that the        vertical-to-horizontal aspect ratio of the LED chip is larger        than 5%.    -   The absorption coefficient of the Group III-nitride film is        lower than 10 cm⁻¹, than 1 cm⁻¹.

FIG. 19 shows a light emitting diode device having a top surface regionwith a textured surface characterized by a surface roughness of about 80nm to about 10,000 nm; and a lateral surface region having a texturedsurface characterized by a surface roughness of about 80 nm to about10,000 nm. As an option, the present light emitting diode device may beimplemented in the context of the architecture and functionality of theembodiments described herein. Or, the present light emitting diodedevice or any characteristic therein may be preset in any desiredenvironment. FIG. 19 shows a light emitting diode device having n-typematerial overlying an active region, in turn overlaying p-type epitaxialmaterial. An n-contact is coupled to the n-type epitaxial material and ap-contact is coupled to the p-type epitaxial material. The top surfaceregion has a textured surface characterized by a surface roughness ofabout 80 nm to about 10,000 nm; and at least one lateral surface regionhaving a textured surface characterized by a surface roughness of about80 nm to about 10,000 nm.

FIG. 20 shows light extraction as a function of roughness. Applicationof the surprising results as shown in FIG. 20 yields a technique forfabricating a light emitting diode device having roughened regions.Strictly as an example, fabricating a light emitting diode device havingroughened regions can commence by providing a gallium and nitrogencontaining substrate including a top surface region, a lateral surfaceregion, an n-type epitaxial material overlying a portion of the topsurface region. One or more active regions can be formed overlying then-type epitaxial material, and p-type epitaxial material disposed tooverly the one or more active regions. Then, a first electrode can becoupled to the n-type epitaxial material (or the substrate material),and a second electrode coupled to the p-type epitaxial material.

FIG. 20 shows performance for surface-roughened LEDs where the typicalfeature size of the roughness is varied. As observed in FIG. 20,increasing the feature size beyond 1 μm leads to an improvement inperformance. This can be justified by considering scattering theory:scattering features smaller than the wavelength of light (e.g., ˜400 nm)are in the Rayleigh scattering regime, where scattering increases withfeature size. This leads to the trend observed on FIG. 20. This trend isexpected to saturate as features become larger than 1 μm and scatteringenters a geometric regime. Therefore, FIG. 20 suggests minimum featuresizes for a good surface roughness. Feature sizes larger than 1 μmprovide the best scattering, while feature sizes in the range 100 nm to1 μm provide a decent, although non-optimal, range.

Likewise, there is a practical maximum for the feature size which isdesirable. Features of tens or hundreds of microns become comparablewith the overall shape of the LED and can be impractical to form andhandle. Therefore, the range 1 μm to 10 μm may be considered a preferredrange because it leads to good scattering and is practical.

Various techniques can be used to form singulation regions, and varioustechniques can be used for separating at the singulation regionboundaries. Optimizing said techniques can improve the roughness, andhence the extraction efficiency.

FIG. 21 shows the encapsulation gain measured experimentally on LEDssimilar to those of FIG. 12. FIG. 21 shows the encapsulation gainperformance of devices cleaved with the same method but along twodifferent crystal planes (a- and m-plane, as shown), similar to thedevices of FIG. 12. Encapsulation gain is an indirect measure ofextraction efficiency; a lower encapsulation gain indicates a higherextraction efficiency. FIG. 21 shows that a cleave along the a-plane,which produces deeper vertical roughness in the LED's sidewalls, leadsto a lower encapsulation gain. The high encapsulation gain for smoothsidewalls 2102 (m-plane cleave) compares favorably to the lowencapsulation gain for striated sidewalls 2104 (a-plane cleave).

FIG. 22 compares SEM images of LED devices obtained by two singulationtechniques. Each of the images shows a singulated LED having a topsurface 2210, a bottom surface 2220, and a plurality of sidewalls 2230,at least one of said sidewalls 2230 comprising at least a first portion2231 having a first texture and comprising at least a portion oflaser-machined surface defined by a laser, and a second portion 2232having a second texture, wherein at least one of said first and secondtextures are different or said first and second portions are non-planar.

The devices in FIG. 22 were singulated by using a laser scribing processfollowed by a breaking process. The two devices employed two methods.Each method uses a different laser beam profile during the laserscribing. Method 1 uses a multiple-beam profile; method 2 uses asingle-beam profile. Due to the successive effect of the multiple beamsas they are rastered along the scribing line, method 1 produces a strong2-dimensional roughness 2202 in the laser-ablated region of firstportion. Method 1, on the other hand, produces a moderate 2-dimensionalroughness 2206 in the first portion.

In general, the parameters of the laser scribing process (such as thelaser beam profile, rastering, pulse width and power) may be optimizedto enhance the roughness in the laser-ablated region (e.g., see FIG. 28)

FIG. 23 compares the lumen output performance of white LEDs whose LEDchips were obtained by two singulation techniques, as shown on FIG. 22.FIG. 23 shows that the LED produced by method 1 leads to a high lumenoutput for strong 2D roughness 2302 as compared with the shown lowerlumen output for moderate 2D roughness 2304.

FIG. 24A is a sketch of the laser beam profile of a laser-ablation tool.Such a profile may be used for fabricating embodiments of the invention.FIG. 24A shows a laser beam profile 2404 composed of several beams. Thismultiple-beam profile is rastered across a singulation direction.Rastering the same area of the semiconductor 2402 leads to a morepronounced roughness.

Some specifications according to some embodiments:

-   -   Vertical-to-horizontal chip aspect ratio >5%.    -   Average lateral size of rough features between 1 μm and 10 μm.    -   Average vertical size of rough features between 100 nm and 10        μm.    -   Average surface coverage of 2-dimensional rough features: top        surface >0.5, sidewall >0.15.    -   A combination of sidewall and surface roughness, such that for        any polar angle at least one of the surfaces has a one-bounce        extraction efficiency into the outside medium larger than 10%.    -   Base shape of the LED can be a square, a triangle, a        parallelogram.    -   The absorption coefficient of the Group III-nitride film is        lower than 10 cm⁻¹. The embodiment of FIG. 18 describes the        impact of absorption coefficient on extraction efficiency.        Alternatively, some embodiments are characterized where the        product of the typical chip dimension, and of the substrate        coefficient, is smaller than 0.1. This can be understood to mean        that the typical absorption through one light bounce in the chip        will be less than 10%.

FIG. 24B and FIG. 24C depict variations in chip shape geometry andcorresponding impact on light extraction. The geometry diagram 24B00 asshown in FIG. 24B depicts a shaped LED device showing height k andvertical sidewall angle Ψ of a tetragonal chip (e.g., having atriangular base). As the height k increases, the vertical sidewall angleΨ decreases, with the vertical sidewall angle Ψ approaching zero for alarge value of height k (e.g., while holding the independent geometricvariables constant).

FIG. 24C depicts a light extraction plot 24C00 as plotted across ofrange of chip shape geometries. As shown, the amount of light extractionis given in the range gradient, with range gradient ranges from about0.6 (60%) to about 0.85 (85%) as shown. The highest light extraction canbe obtained when vertical sidewall angle Ψ is about 10° to about 25° andfor a height k>200 μm. The corresponding highest light extraction rangeis shown in area 2412. The line 2410 corresponds to the maximum value ofk for a given vertical sidewall angle Ψ. The base width is shown asvalue b (which is 380 μm in the case of FIG. 24C). In exemplaryembodiments, the value of b is in the range from about 50 μm to about 5mm.

FIG. 25 depicts a wafer having fabricated LEDs with contacts 2502disposed on the substrate surface 2504. In one embodiment, the LEDs arefabricated with contacts to the n-substrate and p-epi on the samesurface, in a flip-chip configuration. The fabrication consists ofmultiple lithography, etch, metal deposition, and dielectric passivationsteps to form the LED. After the fabrication of the LED device, thewafer is mounted with the metal contacts protected and the backside ofthe wafer exposed. In one embodiment, the wafer may be thinned andpolished, for example by grinding, lapping, and polishing techniques,after mounting on a tape or carrier substrate such as sapphire. Afterpolishing, the LED metallization pattern is visible through the back ofthe wafer as depicted in FIG. 25.

FIG. 26 shows a laser machining technique to form grooves/recesses inthe wafer, thereby defining the scribe lines of singulation. Theversatility of the laser facilitates a wide variety of recessconfigurations. For example, the recess may be a continuous groove, orit may comprise a series of non-continuous recesses—e.g., pits thatprovide a “perforation” line to facilitate singulation. In thisembodiment, the laser scribing results die that has a truncatedtetrahedral shape. The polished side of the wafer is exposed to a laserthat ablates away a portion of the material in the regions near the edgeof the die. A laser is scanned along the edges of each die, shown asslice 1, slice 2, and slice 3 so that a portion of the material alongthe edge of the LED is removed. The laser can be used to scribe, andmultiple passes (e.g., laser scribe pass 1 2602, laser scribe pass 22604 and additional laser scribe passes (e.g., slice 1 2608, slice 22610 and slice 3 2612) can be performed so as to result in singulateddie that each have a truncated tetrahedral shape. Multiple beams 2606can be used to achieve sidewall shaping. Various techniques involvingmultiple beams are shown and discussed as pertaining to the followingFIG. 27.

FIG. 27A depicts a method of scanning the laser to produce a die thathas a shaped sides wall. The first portion of the sidewall which isdefined at least in part by the recess, may also be configured indifferent ways, owing again to the versatility of the laser beam whichmay have a uniform power profile across the beam, or a non-uniform inpower across its beam to shape the laser-machined surface. Additionally,the laser-machined surface can be prepared using multiple passes acrossthe wafer to create a shaped laser-machined surface. Accordingly, therecess may be straight (e.g., V-groove), curved (e.g., U-groove) ormultifaceted such that the first portion is likewise straight, curved ormultifaceted/terraced.

In the particular embodiment of FIG. 27A, a truncated tetrahedral shapeis dislcosed. The laser beam is split into multiple beams with asequence of different powers so as to produce ablation of differentdepths of material. Alternately, the same beam can be scanned multipletimes along adjacent paths, adjusting the beam power for each pass. Asshown, a first laser beam can be configured with a power to ablatethrough material to form a first terrace 2704 ₁, a second laser beam canbe configured with somewhat more power to ablate through more materialto form a second terrace 2704 ₂, a third laser beam can be configuredwith still more power so as to ablate through still more material toform a third terrace 2704 ₃, and so on. The shaped die can include atriangular facet 2705, which can in turn be used as an area fordeposition of electrically-conductive contact material. The number andjuxtaposition of the terraces can be controlled by controlling materialremoval from the bulk substrate. Furthermore, the number andjuxtaposition of the terraces can be controlled so as to result in arelatively larger or relatively smaller triangular facet 2705. Atriangular facet 2705 can approximate a mesa, or a triangular facet 2705can approximate a point-like triangular facet 2705.

The shaped die can be singulated using one or more scribes (e.g.,central scribe 2702).

FIG. 27B, depicts a shaped die with a laser-scribed recess, which inthis embodiment is a groove. The versatility of the laser facilitates awide variety of recess configurations. For example, the recess may be acontinuous groove or it may comprise a series of non-continuousrecesses—e.g., pits that provide a “perforation” line to facilitatesingulation. The first portion of the sidewall which is defined at leastin part by the recess, may also be configured in different ways, owingagain to the versatility of the laser beam which may have a uniformpower profile across the beam, or a non-uniform in power across its beamto shape the laser-machined surface. Accordingly, the recess may bestraight (e.g., V-groove), curved (e.g., U-groove) or multifaceted suchthat the first portion is likewise straight, curved or multifaceted.Additionally, the laser-machined surface can be prepared using multiplepasses across the wafer to create a shaped laser-machined surface.

Referring back to FIG. 27B, a wafer can be processed to produce shapeddice that have a truncated tetrahedral shape. In this embodiment, thelaser machined surface has terraces or grooves resulting from theexposure to the beam profile as shown in FIG. 27A. The angle of thesegrooves can be adjusted to optimize the light extraction. For example,the angle of the grooves can be controlled by adjusting the power ineach of a set of beams and by adjusting the separation (e.g., pitch)between beams. The power may be adjusted by an optical element, or byadjusting the pulse width or period, or both. In one embodiment, thelaser beam profile (e.g., a profile of spatial power distribution of thelaser from each beam) can comprise a power profile having variationsthat are separated sufficiently so as to produce distinct terraces.

FIG. 27C depicts results of using one or more etching technique and/orone or more etching steps. Referring to the view 27C00 of FIG. 27C, awafer can be processed by etching to produce a die with terraces thathave been planarized between terrace levels. Accordingly, the sidewallsof the truncated tetrahedral shape can become substantially planar.Strictly to disclose examples of processing variables:

-   -   The thickness of the wafer can be measured from the epi face        2710 to the substrate face 2700.    -   Terraces can be formed in various pitches, ranks and depths.    -   As examples, given a wafer thickness of 150 um and given a pitch        between laser beams=20 um, and given rank=5, then embodiments        support depths of {20 um, 40 um, 60 um, 80 um, 100 um} or, if        rank=4 then depths might be {25 um, 50 um, 75 um, 100 um}, or,        if rank=4, then depths might be {30 um, 60 um, 90 um, 120 um},        etc.    -   The angles of structures forming the terraces can be reduced by        etching.    -   The laser pitch and depth selected may require more or less time        in post-ablation processing. A closer laser pitch requires less        time to etch, but more time to scribe.    -   Using the disclosed laser ablation techniques, sidewalls can be        formed to incline at any angle between about 10 degrees and        about 70 degrees.

The aforementioned processing techniques to produce shaped dice thathave a truncated tetrahedral shape with terraced or slanted sidewallsare merely examples. Other thicknesses of the wafer, other ranks, otherdepths of the ablation by the laser are reasonable, and do not departfrom the scope of the invention. Strictly as one more example ofreasonable ranges, the starting wafer can be of a thickness from 50 umto 300 um thick, the scribes formed by removal of material (e.g., bylaser ablation) can be about 5 um wide and can range in depth (as shown)over a wide percentage of the wafer depth. In some cases the depth of atrench is as deep as 90% of the thickness of the wafer, in some cases,the depth of a trench is as shallow as a few percent of the thickness ofthe wafer. After laser scribing, the resulting shape of the die includesundulations (e.g., material has been removed by ablation) and a patternof spires that are present between undulations. The spires can be etchedaway using hot KOH, resulting in a smoothing effect over the spires.Continued etching serves to further smooth the spires, which, after acontrolled time period of etching, results in a sloped surface that formslanted sidewalls of the truncated tetrahedral shape.

Using such techniques, the slanted sidewalls can be formed to incline atany angle between about 10 degrees and about 70 degrees. As can beunderstood by those of ordinary skill in the art, the pitch betweenlaser emitters that form the laser beam profile need not be uniformly orperfectly spaced. Moreover, the power delivered by the laser emittersthat form the laser beam profile need not be uniformly or perfectlystaggered.

FIG. 28 shows process for using a staggered laser beam profile depictingvariation of pulse width and power. Use of such a staggered laser beamprofile 2802 can produce die having a truncated tetrahedral shape, suchas is depicted in FIG. 29. Many such die can be produced on one wafer,and the die can be singulated using a shallow scribe. The shown laserbeam profile 2802 is merely one particular configuration using oneparticular group of settings. A laser beam profile can be practiced byuse of multiple laser emitters (e.g., each with an adjacent powerconfiguration), or a laser beam profile can be practiced by use ofmultiple optical elements that serve to attenuate laser beam power takenfrom just one laser emitter. Further, any combination of one or morelaser emitters and one or more optical elements can be used in anycombination so as to produce multiple beams, each having an adjacentpower setting.

FIG. 29 shows a side view of a wafer during processing to produce a diethat has a truncated tetrahedral shape. In this embodiment, a secondlaser machining process is added to produce a shallow scribe 2904 on theside of the wafer with contacts. In one embodiment, the break process isapplied such that the fracture separating the wafer into individual diestarts near the side of the wafer with the shallow scribe so as toprevent the fracture from intersecting the LED device layers. Thesurfaces of such sidewalls are often roughened as a consequence of usingthe aforementioned GaN processing steps. Additionally, the surfaces ofsuch sidewalls can be roughened using additional etching steps. The diecan be singulated by any known method, including the methods as follows:

-   -   The wafer can be flipped over so as to expose the epi face 2710,        and a shallow scribe can be made so as to facilitate singulation        of the tetrahedral shaped die (also see FIG. 26).    -   The wafer can remain substrate face up, and a shallow scribe can        be made so as to facilitate singulation of the tetrahedral        shaped die (also see FIG. 26).    -   It is also possible to cingulate (e.g., fully or partially)        before starting the terracing processes.

As aforementioned, some of the surfaces of a die (e.g., the slantedsidewalls) can be roughened using chemical techniques. Additionally, incertain situations, the processes of singulation can result in a base(e.g., see FIG. 24A, FIG. 24B, and FIG. 24C). The base might bestriated, or might be subjected to processes so as to roughen thesurfaces of the base.

FIG. 30 exemplifies surface roughness when photo-electrochemicaltechniques are used to roughen a face of an LED die. In this instance,the nitrogen face of the die is exposed to 9% KOH at 60° C. for 30minutes, under illumination by an above-bandgap lightsource. Theillumination accelerates the etching rate, and the m-plane facets arepreferentially exposed due to their lower etching rate.

FIG. 31A exemplifies roughness when a lower concentration SAH chemicaletching is used instead of illumination techniques to roughen a face ofan LED die. In this embodiment, illumination is not used in theroughening of the nitrogen face of GaN. Instead, the polished nitrogenface is exposed for to a solution of KOH at 60° C. with an additive toproduce a high density of roughening nucleation sites. In oneembodiment, the additive is silicic acid hydrate at 4.6 g per 120 mL of9% KOH. In another embodiment, the additive is silica gel. Afterexposure to this pre-roughening solution, the wafer may be exposed tohydrochloric acid or another acid to adjust the roughness nucleationsite density. In FIG. 31A, the wafer has been exposed to 37% HCl for 5minutes, although other chemicals, concentrations and times can be usedto obtain the desired roughness scale (depth and pitch). After exposingto silicic acid hydrate to initiate the roughness nucleation points,then adjusting further with hydrochloric acid, the wafer is finallyroughened in 9% KOH at 60° C. for 30 minutes to produce the surfaceroughness seen in FIG. 31A.

FIG. 31B exemplifies roughness when a higher concentration of silicicacid additive (14.6 g in 120 mL of 9% KOH) is used to create theroughening nucleation sites. In this Figure, the procedure was the sameas in FIG. 31A except for the concentration of silicic acid hydrate inKOH: 5 minutes in 9% KOH with 14.6 g silicic acid hydrate at 60° C., 5minutes in 37% HCl at 25° C., and 30 minutes in 9% KOH at 60° C. In allinstances there was no illumination of the wafer during roughening. Ascan be seen by comparing FIG. 31A and FIG. 31B, the roughness scale canbe controlled by the process conditions to optimize the lightextraction.

FIG. 32 shows aluminum etch rates across a range of silicic acid hydrateconcentrations in KOH. In some embodiments of LED fabrication, it isdesirable to have exposed aluminum contacts during the rougheningprocess. However, aluminum is rapidly etched away in KOH-watersolutions. The figure shows that through increasing the concentration ofsilicic acid hydrate the removal of aluminum can be controlled such thatthe roughening process is made compatible with aluminum contacts.

FIG. 33 is a rendering of a triangular die formed using certain of thedisclosed techniques.

FIG. 34A presents an elevated top view of a terraced tetragonal LED chipformed by various laser ablation techniques. The shown embodiment hasterraces of varying widths. The terraces nearer to the triangular facet2705 are slightly narrower than the terraces near the base.

FIG. 34B presents an elevated top view of a slanted sidewall tetragonalLED chip formed by various laser ablation techniques. The shownembodiment has three slanted sidewalls, each of which form an inclinebetween the base and the triangular facet. The slanted sidewalls mightbe roughened by any of the aforementioned etching techniques.

FIG. 34C presents an elevated top view of an undulating slanted sidewalltetragonal LED chip formed by various laser ablation and etchingtechniques. The shown embodiment has three instances of an undulatingslanted sidewall 2701, each of which forms an incline between the baseand the triangular facet. The undulating slanted sidewalls might beroughened by any of the aforementioned etching techniques.

An optical device can be formed using a die having the shape as isdepicted in FIG. 34C. In some cases the undulating slanted sidewallssweep-out two undulations. In some cases the undulating slantedsidewalls sweep-out more than two undulations. Areas or portions ofareas (e.g., regions) that are formed by the at least two undulationsare both substantially curved (as depicted). In other embodiments, twoor more regions that are formed by the at least two undulations are eachsubstantially planar (see FIG. 27B).

FIG. 34D presents a side view of an undulating slanted sidewalltetragonal LED chip formed by various laser ablation and etchingtechniques. The shown embodiment has undulating slanted sidewalls, eachof which instance of the undulating slanted sidewall 2701 form anincline, at least a portion of which is inclined between the plane ofthe epi face 2710 and the plane of the substrate face 2700. Theundulating slanted sidewalls might be roughened by any of theaforementioned etching techniques.

In some embodiments, the variation of undulation over the incline issuch that the angle swept out by a normal line segment or normal ray(e.g., normal ray 3441 ₁ and normal ray 3441 ₂) sweeps out at least 4.5degrees. Variations in the angle swept out by a normal line segment ornormal ray (e.g., see sweep angle1 3431 and sweep angle2 3432) affectslight extraction. In some cases, application of the aforementioned laserablation techniques and etching techniques produces a shaped die havingundulating inclined sidewalls that are composed of only convex portionssuch that the angle swept out by a line segment that is normal to theundulations sweeps out an angle that is 90 degrees or less.

FIG. 35 depicts steps in a method for forming a volumetric LED chipusing laser ablation and scribing processes. As shown, the processingsteps include:

-   -   Provide a gallium and nitrogen containing substrate (see step        3510). The substrate may have completed some or all processing        of contacts, dielectrics, vias, and solder deposition. If not        complete, additional steps may be performed to complete device        fabrication after the roughening and before the final        singulation.    -   Perform a pre-scribe operation over at least a portion of a        wafer (see step 3520). This pre-scribe may have a depth of only        a few microns, or up to a significant fraction or percentage of        the wafer thickness such as 30%. One purpose is to serve as a        stress concentration point for later singulation operations,        such that the fracture that separates the chips passes along the        pre-scribe as opposed to through layers of the device. The        critical geometry of the pre-scribe is the sharpness of the tip,        the depth of the pre-scribe, and the aspect ratio of the        pre-scribe, i.e. the depth of the pre-scribe divided by the        largest opening. The pre-scribe may be formed by a laser        ablation method or by other dry etching methods such as        inductively-coupled plasma (ICP) etching that are able to        produce a deep, narrow trenches. The pre-scribe could be created        after the roughening and demount, but it may be preferred to do        it before wafer thinning when the wafer is less fragile.    -   Perform lap/grind and polish operations on the wafer (see step        3530). The final thickness is chosen in conjunction with the die        dimensions and sidewall slope to optimize extraction while        providing a conductive layer for current spreading. For example,        the final thickness after polishing might be 150 microns.    -   Perform laser scribing to remove material in a staggered pattern        (see step 3540)    -   Perform etching to remove additional material (see step 3550).        This etching includes removal of laser slag, which may require        chemicals other than typically used for GaN roughening/etching.        For instance, one such chemical to remove laser slag is        potassium ferricyanide. GaN etching may be accomplished in        concentrated or dilute basic solutions at elevated temperatures        and/or with illumination to increase the etch rate    -   Perform roughening of the inclined or sloped sidewalls (see step        3560), including roughening of the top flat mesa portion if        present. This can also be accomplished in basic solutions, with        the possible addition of chemical pretreatments (silicic acid,        hydrochloric acid) to control the density of the roughening.    -   Perform demounting and breaking to cingulate into individual        volumetric, tetragonal LED chips (see step 3570). The demounting        refers to removing the wafer from a mechanical support material        if needed, e.g. by dissolving a wax mount or other such wafer        mounting techniques. The singulation step applies a mechanical        force to propagate a crack between the pre-scribe and the        roughened/sloped surface. This is accomplished by, for instance,        striking one side of the wafer with a breaker bar while holding        fixed the other surface, or by applying a stretching force to a        wafer mounted on a stretchable tape.

Descriptions of Exemplary Embodiments

According to an embodiment, the present disclosure relates to atechnique where the side roughness is formed by cleaving/sawing thechip.

According to an embodiment, the present disclosure relates to atechnique where the side roughness is formed by chemical or PEC etching.

According to an embodiment, the present disclosure relates to atechnique where the side roughness is formed by patterning and dryetching of the chip.

According to an embodiment, the present disclosure relates to atechnique where the side roughness if formed by separation of thedevices by laser ablation of the material in-between, followed byetching of the laser process by-products inducing a 2-D roughness on thecrystalline face of the device.

According to an embodiment, the present disclosure relates to atechnique where the side roughness is formed by depositing a film (suchas a dielectric) on the side of the LED and texturing it.

According to an embodiment, the present disclosure relates to atechnique where slanted sidewalls are formed by laser scribing withmultiple beams.

According to an embodiment, the present disclosure relates to atechnique where a Group III-nitride layer is grown on a foreignsubstrate (and possibly separated from the foreign substrate) such thatthe vertical-to-horizontal aspect ratio of the Group III-nitride layeris at least 5%, and LEDs with top and sidewall roughness are formed.

According to an embodiment, the present disclosure relates to atechnique where a layer of a Group III-nitride substrate is separatedfrom the rest of the substrate such that the vertical-to-horizontalaspect ratio of the resulting Group III-nitride layer is at least 5%,and LEDs with top and sidewall roughness are formed.

In one embodiment, a plurality of light emitting diode devices isprovided overlying a bulk-GaN containing substrate. Through suitablefabrication steps, a plurality of p-type metallic ohmic contacts isprovided overlying the p-type GaN layer of the light emitting diodedevice structure, as part of the embodiment. Additionally, a pluralityof n-type ohmic contacts is provided overlying the n-type GaN layer ofthe light emitting diode device structure, as part of the embodiment.

In an embodiment, the plurality of light emitting diode devices issingulated into individual chips using wafer sawing or dicing, where thewafer sawing or dicing induces a surface texture or roughness on thesidewalls of the singulated light emitting diode chips, where thesurface texture or roughness has a characteristic pattern, pitch orshape which enhances the extraction of light from the light emittingdiode chip. In one embodiment, a suitable wet chemical etching step maybe applied after the wafer sawing or dicing step, so as to form a secondtexture or roughness characterizing the plurality of surfaces exposed tothe wet etching step, where the second surface texture or roughness hasa characteristic pattern, pitch or shape which enhances the extractionof light from the light emitting diode chip.

In another embodiment, the plurality of light emitting diode devices issingulated into individual chips using laser scribing followed bybreaking, where the laser scribing induces a surface texture orroughness on the sidewalls of the singulated light emitting diode chips,where the surface texture or roughness has a characteristic pattern,pitch or shape which enhances the extraction of light from the lightemitting diode chip. In an particular embodiment, a suitable wetchemical etching step may be applied between the laser scribing andbreaking steps, in order to remove the slag formed as a result of thelaser scribing, and this wet etching step may result in a second textureor roughness characterizing the plurality of surfaces exposed to the wetetching step, where the second surface texture or roughness has acharacteristic pattern, pitch or shape which enhances the extraction oflight from the light emitting diode chip.

In another embodiment, the plurality of light emitting diode devices aresingulated into individual chips by fully ablating the substratematerial between devices utilizing a laser. The laser ablation processinduces a rough surface of slag and crystalline material on the sidefaces of the chips. The slag material can be etch away to prevent lightabsorption and retain only the roughness from the crystalline material.Alternatively, the slag itself can be used as a mask in conjunction withetching to imprint the roughness on the crystalline material followed bythe removal of the slag material.

In another embodiment, the plurality of light emitting diode devices issingulated into individual chips using diamond scribing and breaking,where the diamond scribing and breaking step induces a surface textureor roughness on the sidewalls of the singulated light emitting diodechips, where the surface texture or roughness has a characteristicpattern, pitch or shape which enhances the extraction of light from thelight emitting diode chip. In an embodiment, the diamond scribing andbreaking may be performed along a direction or a plurality of directionswhich are substantially misaligned with respect to a crystallinedirection or a plurality of crystalline directions of the GaN-containingsubstrate.

In another embodiment, the diamond scribing and breaking may beperformed along a direction or plurality of directions which aresubstantially aligned with respect to a crystalline direction orplurality of crystalline directions of the GaN-containing substrate.

In yet another embodiment, the plurality of light emitting diode devicesis singulated into individual chips using diamond scribing and breaking.In this embodiment, a suitable wet chemical etching step may be appliedbetween the diamond scribing and breaking steps, so as to form a secondtexture or roughness characterizing the plurality of surfaces exposed tothe wet etching step, where the second surface texture or roughness hasa characteristic pattern, pitch or shape which enhances the extractionof light from the light emitting diode chip.

In an embodiment, the diamond scribing and breaking may be performedalong a direction or a plurality of directions which are substantiallymisaligned with respect to a crystalline direction ora plurality ofcrystalline directions of the GaN-containing substrate. Alternatively,the diamond scribing and breaking may be performed along a direction orplurality of directions which are substantially aligned with respect toa crystalline direction or plurality of crystalline directions of theGaN-containing substrate. That is, the scribing is performed along atleast one direction or a plurality of directions that are substantiallymisaligned with respect to a crystalline direction or a plurality ofcrystalline directions plane of the gallium and nitrogen containingsubstrate. In an embodiment, the direction is substantially misalignedis within ±5 degrees or ±10 degrees or ±20 degrees of the plane of thegallium and nitrogen containing substrate. As used herein, the termmisaligned is provided intentionally and is generally an offset or thelike. Depending upon the embodiment, the plane of the gallium andnitrogen containing substrate is one of a plurality of planes of thesubstrate material selected from a group consisting of at least c-plane,m-plane, or a-plane or others and their combinations, and semipolarplanes. Again, there can be other variations, modifications, andalternatives.

In an embodiment, the characteristic texture or roughness may besubstantially dissimilar across the plurality of surfaces formed as aresult of the light emitting diode device singulation process. In yetanother embodiment, the characteristic texture or roughness may besubstantially similar across the plurality of surfaces formed as aresult of the light emitting diode device singulation process.

In an embodiment, no specific means or methods are applied to apply asurface texture or roughness to the surface or plurality of surfaces ofthe light emitting diode device chip which are overlaid by the p-typemetallic contact or n-type metallic contact or both. In anotherembodiment, means or methods are applied to apply a surface texture orroughness to the surface or plurality of surfaces of the light emittingdiode device chip which are overlaid by the p-type metallic contact orn-type metallic contact or both.

The foregoing description of the exemplary embodiments has beenpresented only for the purposes of illustration and description and isnot intended to be exhaustive or to limit the invention to the preciseforms disclosed. Many modifications and variations are possible in lightof the above teaching.

The embodiments were chosen and described in order to explain theprinciples of the invention and their practical application so as toenable others skilled in the art to utilize the invention and variousembodiments and with various modifications as are suited to theparticular use contemplated. Alternative embodiments will becomeapparent to those skilled in the art to which the present inventionpertains without departing from its spirit and scope. Accordingly, thescope of the present invention is defined by the appended claims ratherthan the foregoing description and the exemplary embodiments describedtherein.

In the foregoing specification, the disclosure has been described withreference to specific embodiments thereof. It will, however, be evidentthat various modifications and changes may be made thereto withoutdeparting from the broader spirit and scope of the disclosure. Forexample, the above-described process flows are described with referenceto a particular ordering of process actions. However, the ordering ofmany of the described process actions may be changed without affectingthe scope or operation of the disclosure. The specification and drawingsare, accordingly, to be regarded in an illustrative sense rather than ina restrictive sense.

What is claimed is:
 1. A method of fabricating LEDs from a wafercomprising a substrate and epitaxial layers and having a substrate sideand a epitaxial side, said method comprising: applying a laser beamacross at least one of said substrate side or said epitaxial side ofsaid wafer to define at least one laser-scribed recess having alaser-machined surface; and singulating said wafer along saidlaser-scribed recess to form singulated LEDs, said singulated LEDshaving a top surface, a bottom surface, and a plurality of sidewalls, atleast one of said sidewalls comprising at least a first portion having afirst texture and comprising at least a portion of said laser-machinedsurface, and a second portion having a second texture, wherein at leastone of said first and second textures are different or said first andsecond portions are non-planar.
 2. The method of claim 1, wherein saidsecond portion is orthogonal to said top surface.
 3. The method of claim2, wherein first portion is defined along a non-crystallographic planeof said substrate, and second portion is defined along acrystallographic plane of said substrate.
 4. The method of claim 1,wherein said first texture comprises terraces and said second texturecomprises vertical striations.